Digital video compression and decompression systems are generally required to comply with the applicable standards in order to ensure interoperability with other products following the same standards. Video compression standards are continuing to evolve, and as they do so they are becoming more complex. At the same time, the performance requirements of digital video decoders (“decoders”) and digital video encoders (“encoders”) are increasing, to support high definition and other requirements and the performance requirements are compounded by the growing complexity of the video standards. Also, cost pressures on video decoders and encoders is tremendous, and the increased complexity and performance needs to be provided in very small and low power implementations in order to meet the cost objectives.
The issues of performance, complexity and cost in decoders and encoders may be further compounded by certain details of some video standards. In some cases, new video standards are developed by a process of algorithmic analysis and experimentation and development of software that runs on fast general purpose processors, such as the latest generation of personal computers. When such algorithms are ported to low cost, low power devices that are suitable for mass production, often problems arise resulting from the lack of suitability of the algorithms to such devices.
Low cost decoders and encoders generally use pipelined architectures in order to achieve the required levels of performance in reasonable device sizes and with reasonable power requirements, which generally dictate modest clock rates. Pipeined designs generally split different functions into different stages as well as into different modules. Each, module may use multiple pipeline stages. Some video formats have aspects which are incompatible with pipelined decoder and encoder architectures.
An example of such an incompatibility is the HYBRIDPRED syntax element in the SMPTE VC-1 draft standard and also in the Microsoft Windows Media Video 9 format, which is similar to VC-1 (previously known as VC-9). The presence of the HYBRIDPRED syntax element is conditional and it depends on the values of reconstructed luma motion vectors, which are generally processed in a later pipeline stage than the processing of the input bit stream in a pipelined decoder design. Therefore it is generally not possible to parse the input bit stream in one pipeline stage and reconstruct motion vectors in a subsequent pipeline stage, due to the aforementioned dependency. A representative specification of the SMPTE VC-1 draft standard is C24.008-VC1-Spec-CD1r5.pdf. The process of hybrid motion vector prediction using the HYBRIDPRED syntax element is specified in section 8.3.5.3.5.
In other designs, there is one processor performing essentially all decoding functions. A primary example is a personal computer executing software to decode digital video. With one processor performing all decoding functions, operations such as entropy decoding and motion vector reconstruction are naturally performed at different times as the processor executes different parts of the software, and the dependency of entropy decoding on the reconstructed motion vectors is met by having the processor reconstruct motion vectors as needed before parsing the HYBRIDRED syntax element. Such designs are not referred to herein as being pipelined.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.